Kforce has a client seeking an ASIC Verification & Validation Engineer in Milpitas, CA.
The ASIC Verification and Validation Engineer will work on verification of RTL functionality towards the development of the company's next generation eSSD SOC SSD controllers. As a Verification Engineer, the daily activities would include debugging Chip Level SoC RTL simulations to find functional bugs, working with the RTL design team to fix the bugs, reading design specs and developing/executing test plans, functional coverage points, monitors, scoreboards, sequencers, and sequences, which utilize scripts, System Verilog/UVM, C++, and other methodologies to increase the rate at which ASIC bugs are found and resolved. Your contributions will have an immediate contribution to the company's success in our fast paced environment.
- Define and develop the test-bench and test plan for verifying RTL against specification using UVM
- Work with cross function teams to close the gap in the verification plan and needed support
- Review ASIC Verification and Validation plans
- Develop complex test cases that involve control/data paths of multiple IPs at module and chip level
- Responsible for developing, executing and debugging test cases in RTL, Gate Level and FPGA RTL simulation environments
- Report coverage including functional, code and other metrics
- Work closely with ASIC design team to triage and resolve issues
- Improving ASIC verification methodology and driving the adoption
- Interfaces with Architecture, ASIC, and Validation teams through the product technology development phase